Course work for Digital Logic Design. I resurrected this from a folder that must have been untouched for 2 years. You are more than welcome to entertain yourself with it if you had a FPGA. Despite its cringeness, I’m almost proud of that sophomore rookie who finished this within his rations from 11 p.m to 7 a.m. in 4 days.
Overview of the design:
The randomness is generated with LSFR:
And the demo: